Rostock

A digital shift register of the Leibniz Binary Subsystem in 8 HP: eight parallel delay lines of 1 to 64 stages that delay, loop or scramble the 8-bit data passed through the Leibniz ribbon cables at the back, each bit clockable on its own.

Key features

• Pipeline length from 1 to 64 stages, set by the encoder and shown on a two-digit display, voltage-controlled through LENGTH with an adjustable depth (ATT %, 0 to 99)
• LOOP closes the pipeline on itself; SCRAMBLE feeds it the input and output bits combined by XOR; both lit buttons with gate inputs
• CLEAR button and input empty the memory
• Eight clock inputs replace the Leibniz clock bit by bit; OUTG. CLOCK IN replaces the clock passed on to the next modules
• Eight LEDs show the output bits
• No data jacks on the panel: data comes in and goes out through the Leibniz headers at the back