Digital Filter Simulator

Based on ideas in a 1969 IEEE paper, Hybrid Implementation for Sampled-data Controllers, which presents the canonical form of a generalised digital filter made of analogue elements: an analogue circuit, all CMOS and op amps. Incoming audio (or CV, to use it as a pattern generator) is fed to a 4-bit A/D stage (a thermometer scale, or unary code); the 4 bits go through a 4-stage delay (shift registers); each delayed bit is reunited with its siblings in four D/A stages, and the stepped signals are fed back to the input through an attenuator/inverter stage (FEEDBACK) and to the summed output through another (OUTPUT). The clock input ticks over the shift registers: CV on the VCO supplying the clock controls the filter. RANGE needs setting to a suitable level (the maker likes the PEAK LED flickering) and can be controlled by CV, from a 1-bit signal to 4 bits, or overdriving it until everything locks up. Clocks at multiples or divisions of the audio are interesting; fed a gate and a CV it performs as a complex pattern generator.

Key features

• RANGE CV, CLOCK, IN1 and IN2 in; two OUT
• RANGE, with its PEAK LED; five FEEDBACK and five OUTPUT knobs, the attenuator/inverter stages
• 12 HP; Nonlinearcircuits publishes no current draw, depth or assembled price (it sells the DIY PCB and panel), and ModularGrid lists none